HiSilicon · 海思技术有限公司

Fabless

Huawei’s wholly-owned chip design arm, and the entity behind China’s most publicized export-control test case: the Kirin 9000S in the August 2023 Mate 60 P…
Published

October 11, 2026

Chinese name: 海思技术有限公司 (Hǎisī Jìshù Yǒuxiàn Gōngsī)

TipWhy This Matters

Huawei’s wholly-owned chip design arm, and the entity behind China’s most publicized export-control test case: the Kirin 9000S in the August 2023 Mate 60 Pro, fabricated domestically by SMIC at a 7nm-class node despite Huawei itself being Entity List-restricted since 2019. In May 2026, Huawei semiconductor unit president He Tingbo announced at ISCAS 2026 a new ‘logic folding’ (τ/韬 scaling) architecture — stacking two device layers vertically to raise transistor density by a claimed 53.5% — as a way to keep advancing performance without smaller lithography. The Kirin 9050 Pro shipped on 1 October 2026 across the Mate 90 series (claimed +31% overall device performance, first Geekbench results ~1,117/5,076); an updated September 2026 paper claims 41%/58%/66% CPU/GPU/NPU power reductions versus the prior generation at equal performance. On AI, Huawei Connect 2026 (Shanghai, 17 September) unveiled the Ascend 960 SuperPoD — a 4,096-card supernode using near-package optics (Hi-ONE), 8 EFLOPS FP8 — with the roadmap pulled forward: 960DT Q1 2027, Ascend 970 in 2028, 980 in 2029.

What does this firm design?

Full-stack SoCs across smartphone (Kirin), server/PC (Kunpeng, based on ARM architecture licensed before restrictions tightened), AI accelerator (Ascend), and modem (Balong) product lines.

Key Facts

Category Fabless
Founded 2004
Location Shenzhen, Guangdong
Product Focus Smartphone SoCs (Kirin), server/PC CPUs (Kunpeng), AI accelerators (Ascend), modem/baseband (Balong)
Node Sophistication 7nm-class via multipatterning (Kirin 9000S, August 2023); the Kirin 9050 Pro (launched 1 October 2026 in the Mate 90 series) and the rest of that ‘tau-law’ cohort use 3D ‘logic folding’ (dual-layer vertical die stacking) to raise effective transistor density by a claimed 53.5% (238 MTr/mm²) without requiring a smaller lithography node
Entity List Yes — US Commerce BIS
Last Verified Newest source dated 01 Oct 2026 (6 sources)

Design Score

4.8/5

Sources

Back to Design Tracker